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APU0063
PRELIMINARY
80 CH Driver for Dot Matrix LCD
FEATURES
Display driving bias ; static-1/5
GENERAL DESCRIPTION
The APU0063 is a LCD driver LSI that is fabricated by low power CMOS technology. Basically this LSI consists of 40 x 2bit bi-directional shift register, 40 x 2bit data latch and 40 x 2bit driver.
* * * * *
Power supply voltage ; +5V 10% +3V 10% Supply voltage range for display : 10V Negative display voltage : 0 VEE VDD-10V CMOS Process Interface
APPLICATIONS
* * * *
Dot matrix LCD driver with 80-channel output. Input / Output signal Output ; 40 x 2 channel waveform for LCD driving Input ; - Serial display data and control pulse from controller LSI .
Driver (cascade connection) Controller Other APU0065 APU0066
ORDERING INFORMATION
APU0063 E
Handling Code Package Type Q : QFP Y : Chip Handling Code TY : Tray Package Type
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 1 www.anpec.com.tw
APU0063
PRELIMINARY
V1 V2 V3 V4 SC41~SC80
SC1~SC40
End Stage Output Voltage Multiplexor Part1
V 1S V 2S
Pre-Stage Output Voltage Multiplexor Part1
V 1S V 2S
End Stage Output Voltage Multiplexor Part2
PART 1
PART 2 latch clock
LATCH part1
LATCH part 2
register clock DL1 SHIFT part 1 SHIFT part 2 DR2
SHL1
DR1
CL1
M
CL2
DL2
SHL2
Figure 1.Block diagram of APU0063
Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002
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S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 S71 81 S72 82 S73 83 S74 84 S75 85 S76 86 S77 87 S78 88 S79 89 S80 90 S40 91 S39 92 57 56 55 54 53 52
51
50 NC
49 NC
48 M
47 DR2
46 DL2
45 DR1
44 DL1
43 CL2
42 V D D
APU0063
41 NC
40 NC
39 SHL2
PRELIMINARY
S38 93 S37 94 S36 95 S35 96 S34 97
38 SHL1
37 CL1
36 GND
34 V 3
APU0063
S33 98 S32 99 S31 100 1 2 3 4 5 6 7 8 9 10 11 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 12 13 14 15 16 17 18 19 20 21 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 22 S9 23 S8 24 S7 25 S6 26 S5 27 S4 28 S3 29 S2
33 V 2
32 V 1
31 V E E
30
S1
Figure 2. QFP100 Top View
35 V 4
Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002
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APU0063
PRELIMINARY
PIN DESCRIPTION-QFP100
PIN(NO.)
V E E (31) V D D (42) V S S (36) V 1 ~ V 4 (32 ~ 35) M(48) CL1(37) CL2(43)
INPUT OUTPUT
Power Power Power Input Input Input Input
NAME
Negative Supply Voltage Operating Voltage Operating Voltage Bias Voltage
DESCRIPTION
For LCD driver circuit (0 V E E V D D -10V) For logic circuit (+5V 10% ,+3V 10%) 0 V ( G N D) Bias Voltage level for LCD drive
INTERFACE
Power Supply Power Supply Power Supply Power Supply Controller Controller Controller
Altemated Signal for This is the signal for LCD twisting LCD Driver Output Data Latch Clock Data Shift Clock
The signal enable the latch, it is negative senstive latched. The signal enable the shift register, it is negative edge-trigger. Selection of the shift directon of Part1 shift register SHL1 VDD V SS DL1 Output Input DR1 Input Output
SHL1(38)
Input
Shifting Direction Control Signal of Part1
Controller
DL1, DR1 (44, 45) S C 1 ~ SC 40
Input Output Output
Data Interface LCD Driver
Data input / output pf Part1 shift register LCD driver output of Part1 Selection of the shift directon of Part2 shift register SHL2 VDD V SS DL2 Output Input DR2 Input Output
Controller or APU0066 LCD
SHL2(39)
Input
Shifting Direction Control Signal of Part2
Controller
DL2, DR2 (46, 47) S C 41 ~ SC 80
Input Output Output
Data Interface LCD Driver
Data input / output pf Part2 shift register LCD driver output of Part2
Controller or APU0066 LCD
NOTE : Input pin can not be floated,or it will cause large leakage current.
Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002
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APU0063
PRELIMINARY
DRIVER OUTPUT VOLTAGE
A signal of driving pin is the one of V1,V2,V3 or V4.These selecting are following.
D a ta o f la tc h H ig h H ig h Low Low
M H ig h Low H ig h Low
O u tp u t v o lta g e V1 V2 V3 V4
SHIFT DRIRECTION SPECIFICATION
Part1
When Part1 shift direction control signal , SHL1, is set to VSS. Now the Part1 register shift direction is DL1 SC1 SC2 . . . SC39 SC40 DR1 Otherwise,when SHL1 is set to VDD.Its direction is DL1 SC1 SC2 . . . SC39 SC40 DR1
Part2
When Part2 shift direction control signal, SHL2, is set to VSS. Now the Part2 register shift direction is DL2 SC41 SC42 . . . SC79 SC80 DR2 Otherwise,when SHL2 is set to VDD.Its direction is DL2 SC41 SC42 . . . SC79 SC80 DR2
Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002
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APU0063
PRELIMINARY
MAXIMUM ABSOLUTE LIMIT (Ta = 25 C)
Characteristic
Operating Voltage Driver Supply Voltage Input Voltage 1 Input Voltage 2 (V ~ V 4 ) 1 Operating Temperature Storage Temperature
Symbol
V DD V LCD V IN1 V IN2 TO P R TS T G
Value
- 0.3 ~ + 7.0 V DD - 13.5 ~ VDD + 0.3 - 0.3 ~ VDD + 0.3 V DD + 0.3 ~ VE E - 0.3 - 30 ~ + 85 - 55 ~ + 125
Unit
V V V V
o o
C C
Voltage greater than above may damage to the circuit ELECTRICAL CHARACTERISTICS DC characteristics (VDD = 2.7 ~ 5.5V, 0 VEE VDD - 10V, VSS = 0V, Ta = - 30 ~ + 85 C )
Characteristic
Operating Current* Supply Current* Input High Voltage Input Low Voltage Input Leakage Current Output High Voltage Output Low Voltage Voltage Descending
Symbol
ID D IE E V IH V IL I LKC V OH V OL V D1 V D2
Test condition
f CL2 = 4 0 0 K H z f CL1 = 1 KHz _
Min
_ _ 0.7 V D D 0
Max
1 10 V DD 0.3 V D D 5 _
Unit
mA A V A
Applicable pin
_
V IN = 0 - V D D I O H = -0.4 mA I OL = +0.4 mA I O N = 0.1mA for one of SC1-SC80 ION = 0 . 0 5 m A f o r e a c h S C 1 - S C 8 0 V IN = V DD ~ V E E (Output SC1 ~ SC80 : floating)
CL1, CL2, DR1, DR2, DR1, DR2, SHL1, SHL2, M, FCS
-5 V DD - 0.4 _ _ _
DL1, DL2, DR1, DR2 0.4 V 1.1 1.5 10 A V (V 1 ~ V 4 ) SC (SC1 ~ SC80)
Leakage Current
IV
-10
V1 ~ V4
AC CHARACTERISTICS (VDD = 2.7 ~ 5.5V, 0 VEE VDD - 10V, VSS = 0V, Ta= - 30 ~ + 85 C )
Characteristic
Data shift Frequency Clock High Level Width Clock Low Level Width Clock Set-up Time
Symbol
fCL tW C K H tW C K L tSL tLS
Test condition
_ _ _ _ from CL2 to CL1 from CL1 to CL2 _ _ _ CL1=15pF
Min
_ 800 800 500 500 _ 300 300 _
Max
400 _ _ _ _
Unit
KHz
Applicable pin
CL2 CL1, CL2 CL2
CL1, CL2 ns
Clock Rise/Fall Time Data Set-up Time Data Hold Time Data Delay Time
tR / tF tS U tD H tD
200 _ _ 500 DL1, DL2, DR1, DR2, FLM DL1, DL2, DR1, DR2
Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002
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APU0063
PRELIMINARY
TIMING CHARACTERISTICS
V IH tWCKL V IL tR tW C K H tF tD H tS U V IL
V IH
CL2
Data in (DL1,DL2) (DR1,DR2)
V IH V IL
tD
tSL
Data out (DR1,DR2) (DL1,DL2)
V OH V OL V IH V IL tR tSU
tLS
tLS
CL1
tW C K H tF
FLM
V IH V IL
Figure 3.Timing diagram of signals
M
Latch
CL1
Shift
CL2 DL1 / DR1 DL2 / DR2 OUTPUT OF LATCH (SC)
SC1 SC2
SC79 SC80
SC1~SC80
Figure 4.timing diagram
Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002
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APU0063
PRELIMINARY
OUTPUT OF LATCH (DATA)
M
V2 V4 V3
S C 1 ~ S C 80
V1
Figure 5.SC1~SC80 output waveform
APPLCATION CIRCUIT
COM1 ~ COM16
LCD
common signal
APU0066 (controller)
M CLK2 CLK1 D
SHL1 SHL2 FCS DL1 DR1 DL2
S C 1~ S C 80
APU0063 (seg driver)
CL1 CL2
SHL1 SHL2 FCS DR2 M DL1 DR1 DL2
S C 1~ S C 80
APU0063 (seg driver)
CL1 CL2
DR2 M OPEN
Figure 6.Connection between APU0063 and Controller
Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002
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S2 78
S3 77
S4 76
S5 75
S6 74
S7 73
S8 72
S9 71
S10 70
S11 69
S12 68
S13 67
S14 66
S15 65
S16 S17 64 63
S18 62
S19 61
S20 60
S21 S22 59 58
S23 57
S24 56
S25 55
S26 54
S27 53
S28 52
S29 51
S30 50
S31 49
S1
79
48
S32
V
EE
80
47
S33
V
1
81
APU0063
46
S34
V
2
82
45
S35
V
3
83
44
S36
V
4
84
Y
43
S37
GND 85
42
S38
CL1
86
41
S39
SHL1 87
40
S40
SHL2 88
(0,0)
39
S80
V
PRELIMINARY
DD
89
38
S79
CL2
90
37
S78
DL1
91
Chip size : 3438 x 2476 Pad size : 80 x 80 Pad Pitch : 100 ~ 125 Unit : m
36
S77
Note : ( 0 , 0 ) is center in the chip Button left corner coordination is ( -1719 , -1238 ) Top right corner coordination is ( 1719 , 1238 ) Figure 7.Chip pad arrangement
X
DR1 92
35
S76
DL2
93
34
S75
DR2 94
33
S74
APU0063
M
95
32
S73
S41
96
31
S72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 S58
18
19
20
21
22
23
24
25
26
27
28
29
30
S42 S43
S44 S45
S46
S47
S48
S49
S50
S51 S52
S53
S54
S55
S56 S57
S59
S60
S61 S62
S63
S64
S65
S66 S67
S68
S69
S70
S71
Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002
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APU0063
PRELIMINARY
PAD LOCATION (1/2)
PAD NUMBER PAD NAME
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SC42 SC43 SC44 SC45 SC46 SC47 SC48 SC49 SC50 SC51 SC52 SC53 SC54 SC55 SC56 SC57 SC58 SC59 SC60 SC61 SC62 SC63 SC64 SC65 SC66 SC67 SC68 SC69 SC70 SC71 SC72 SC73
COORDINATE X Y
-1645 -1520 -1395 -1270 -1145 -1020 -900 -780 -660 -550 -450 -350 -250 -150 -50 50 150 250 350 450 550 660 780 900 1020 1145 1270 1395 1520 1645 1609 1609 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -1132 -920 -800
PAD NUMBER PAD NAME
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 SC74 SC75 SC76 SC77 SC78 SC79 SC80 SC40 SC39 SC38 SC37 SC36 SC35 SC34 SC33 SC32 SC31 SC30 SC29 SC28 SC27 SC26 SC25 SC24 SC23 SC22 SC21 SC20 SC19 SC18 SC17 SC16
COORDINATE X Y
1609 1609 1609 1609 1609 1609 1609 1609 1609 1609 1609 1609 1609 1609 1609 1609 1645 1520 1395 1270 1145 1020 900 780 660 550 450 350 250 150 50 -50 -680 -560 -450 -350 -250 -150 -50 50 150 250 350 450 560 680 800 920 1132 1132 1132 1132 1132 1132 1132 1132 1132 1132 1132 1132 1132 1132 1132 1132
Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002
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APU0063
PRELIMINARY
PAD LOCATION (2/2)
PAD NUMBER PAD NAME
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 SC15 SC14 SC13 SC12 SC11 SC10 SC9 SC8 SC7 SC6 SC5 SC4 SC3 SC2 SC1 V EE
COORDINATE X Y
-150 -250 -350 -450 -550 -660 -780 -900 -1020 -1145 -1270 -1395 -1520 -1645 -1609 -1609 1132 1132 1132 1132 1132 1132 1132 1132 1132 1132 1132 1132 1132 1132 920 800
PAD NUMBER PAD NAME
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 V1 V2 V3 V4 GND CL1 SHL1 SHL2 V DD CL2 DL1 DR1 DL2 DR2 M S41
COORDINATE X Y
-1609 -1609 -1609 -1609 -1609 -1609 -1609 -1609 -1609 -1609 -1609 -1609 -1609 -1609 -1609 -1609 680 560 450 350 250 150 50 -50 -150 -250 -350 -450 -560 -680 -800 -920
Customer Service
Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369
Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002
11
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